/********************************************************************************
  * @copyright : Metanergy Technology R&D Co., Ltd
  * @filename  :myg0025_rcc.h
  * @brief     :RCC initialization and configuration
  * @author    :AE_TEAM
  * @version V1.0.0/2023-04-08
  * @log  V1.0.0/2023-04-08 Initial release
  *******************************************************************************/


/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MYG0025_RCC_H
#define __MYG0025_RCC_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "myg0025.h"

/** @addtogroup RCC RCC
  * @{
  */


/** @defgroup RCC_Exported_Types RCC_Exported_Types
  * @{
  */
typedef struct
{
    uint32_t SYSCLK_Frequency;
    uint32_t HCLK_Frequency;
    uint32_t PCLK1_Frequency;
    uint32_t I2C1CLK_Frequency;
    uint32_t UART1CLK_Frequency;
    uint32_t UART2CLK_Frequency;
    uint32_t ADCCLK_Frequency;
    uint32_t FLASHCLK_Frequency;
    uint32_t RTCCLK_Frequency;
} RCC_ClocksTypeDef;

/**
  * @}
  */
/* Exported constants --------------------------------------------------------*/

/** @defgroup RCC_Exported_Constants RCC_Exported_Constants
  * @{
  */

/** @defgroup RCC_HSE_configuration RCC_HSE_configuration
  * @{
  */

#define RCC_HSE_OFF                      ((uint8_t)0x00)
#define RCC_HSE_ON                       ((uint8_t)0x01)
#define RCC_HSE_Bypass                   ((uint8_t)0x05)
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
                         ((HSE) == RCC_HSE_Bypass))

/**
  * @}
  */

/** @defgroup RCC_PLL_Clock_Source RCC_PLL_Clock_Source
  * @{
  */

#define RCC_PLLSource_HSI_Div2           ((uint8_t)0x00)
#define RCC_PLLSource_HSE                ((uint8_t)0x10)
#define RCC_PLLSource_HSI                ((uint8_t)0x11)

#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
                                   ((SOURCE) == RCC_PLLSource_HSI)      || \
                                   ((SOURCE) == RCC_PLLSource_HSE))


/**
  * @}
  */

/** @defgroup RCC_LSE_WAIT_TIME RCC_LSE_WAIT_TIME
  * @{
  */

#define RCC_LSE_STAB_WAIT_TIME_NOWAIT    ((uint8_t)0x00)
#define RCC_LSE_STAB_WAIT_TIME_256       ((uint8_t)0x01)
#define RCC_LSE_STAB_WAIT_TIME_1024      ((uint8_t)0x02)
#define RCC_LSE_STAB_WAIT_TIME_4096      ((uint8_t)0x03)
#define RCC_LSE_STAB_WAIT_TIME_8192      ((uint8_t)0x04)
#define RCC_LSE_STAB_WAIT_TIME_16384     ((uint8_t)0x05)
#define RCC_LSE_STAB_WAIT_TIME_32768     ((uint8_t)0x06)
#define RCC_LSE_STAB_WAIT_TIME_65536     ((uint8_t)0x07)




#define IS_RCC_LSE_WAIT_TIME_VALUE(VALUE) (((VALUE) == RCC_LSE_STAB_WAIT_TIME_NOWAIT) || \
                                          ((VALUE)  == RCC_LSE_STAB_WAIT_TIME_256) || \
                                          ((VALUE)  == RCC_LSE_STAB_WAIT_TIME_1024) || \
                                          ((VALUE)  == RCC_LSE_STAB_WAIT_TIME_4096) || \
                                          ((VALUE)  == RCC_LSE_STAB_WAIT_TIME_8192) || \
                                          ((VALUE)  == RCC_LSE_STAB_WAIT_TIME_16384) || \
                                          ((VALUE)  == RCC_LSE_STAB_WAIT_TIME_32768) || \
                                          ((VALUE)  == RCC_LSE_STAB_WAIT_TIME_65536))

/**
  * @}
  */

/** @defgroup RCC_PLL_Multiplication_Factor RCC_PLL_Multiplication_Factor
  * @{
  */

#define RCC_PLLMul_2                    ((uint32_t)0x00 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_3                    ((uint32_t)0x01 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_4                    ((uint32_t)0x02 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_5                    ((uint32_t)0x03 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_6                    ((uint32_t)0x04 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_7                    ((uint32_t)0x05 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_8                    ((uint32_t)0x06 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_9                    ((uint32_t)0x07 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_10                   ((uint32_t)0x08 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_11                   ((uint32_t)0x09 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_12                   ((uint32_t)0x0A << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_13                   ((uint32_t)0x0B << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_14                   ((uint32_t)0x0C << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_15                   ((uint32_t)0x0D << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_16                   ((uint32_t)0x0E << RCC_CFGR_PLLMUL_Pos)

#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3)   || \
                             ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5)   || \
                             ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7)   || \
                             ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9)   || \
                             ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
                             ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
                             ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
                             ((MUL) == RCC_PLLMul_16))
/**
  * @}
  */

/** @defgroup RCC_PREDIV_division_factor RCC_PREDIV_division_factor
  * @{
  */
#define  RCC_PREDIV_Div1               ((uint32_t)0x00 << RCC_CFGR2_PLLPREDIV_Pos)
#define  RCC_PREDIV_Div2               ((uint32_t)0x01 << RCC_CFGR2_PLLPREDIV_Pos)
#define  RCC_PREDIV_Div3               ((uint32_t)0x02 << RCC_CFGR2_PLLPREDIV_Pos)
#define  RCC_PREDIV_Div4               ((uint32_t)0x03 << RCC_CFGR2_PLLPREDIV_Pos)
#define  RCC_PREDIV_Div5               ((uint32_t)0x04 << RCC_CFGR2_PLLPREDIV_Pos)
#define  RCC_PREDIV_Div6               ((uint32_t)0x05 << RCC_CFGR2_PLLPREDIV_Pos)
#define  RCC_PREDIV_Div7               ((uint32_t)0x06 << RCC_CFGR2_PLLPREDIV_Pos)
#define  RCC_PREDIV_Div8               ((uint32_t)0x07 << RCC_CFGR2_PLLPREDIV_Pos)
#define  RCC_PREDIV_Div9               ((uint32_t)0x08 << RCC_CFGR2_PLLPREDIV_Pos)
#define  RCC_PREDIV_Div10              ((uint32_t)0x09 << RCC_CFGR2_PLLPREDIV_Pos)
#define  RCC_PREDIV_Div11              ((uint32_t)0x0A << RCC_CFGR2_PLLPREDIV_Pos)
#define  RCC_PREDIV_Div12              ((uint32_t)0x0B << RCC_CFGR2_PLLPREDIV_Pos)
#define  RCC_PREDIV_Div13              ((uint32_t)0x0C << RCC_CFGR2_PLLPREDIV_Pos)
#define  RCC_PREDIV_Div14              ((uint32_t)0x0D << RCC_CFGR2_PLLPREDIV_Pos)
#define  RCC_PREDIV_Div15              ((uint32_t)0x0E << RCC_CFGR2_PLLPREDIV_Pos)
#define  RCC_PREDIV_Div16              ((uint32_t)0x0F << RCC_CFGR2_PLLPREDIV_Pos)

#define IS_RCC_PREDIV(PREDIV)   (((PREDIV) == RCC_PREDIV_Div1) || ((PREDIV) == RCC_PREDIV_Div2) || \
                                 ((PREDIV) == RCC_PREDIV_Div3) || ((PREDIV) == RCC_PREDIV_Div4) || \
                                 ((PREDIV) == RCC_PREDIV_Div5) || ((PREDIV) == RCC_PREDIV_Div6) || \
                                 ((PREDIV) == RCC_PREDIV_Div7) || ((PREDIV) == RCC_PREDIV_Div8) || \
                                 ((PREDIV) == RCC_PREDIV_Div9) || ((PREDIV) == RCC_PREDIV_Div10) || \
                                 ((PREDIV) == RCC_PREDIV_Div11) || ((PREDIV) == RCC_PREDIV_Div12) || \
                                 ((PREDIV) == RCC_PREDIV_Div13) || ((PREDIV) == RCC_PREDIV_Div14) || \
                                 ((PREDIV) == RCC_PREDIV_Div15) || ((PREDIV) == RCC_PREDIV_Div16))
/**
  * @}
  */

/** @defgroup RCC_System_Clock_Source RCC_System_Clock_Source
  * @{
  */

#define RCC_SYSCLKSource_HSI            ((uint8_t)0x00)
#define RCC_SYSCLKSource_HSE            ((uint8_t)0x01)
#define RCC_SYSCLKSource_PLLCLK         ((uint8_t)0x02)
#define RCC_SYSCLKSource_LSE             ((uint8_t)0x10)
#define RCC_SYSCLKSource_LSI             ((uint8_t)0x11)
#define RCC_SYSCLKSource_HSI48           ((uint8_t)0x12)
#define RCC_SYSCLKSource_HSI12           ((uint8_t)0x13)
#define RCC_SYSCLKSource_EXTCLK          ((uint8_t)0x14)

#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI)   || \
                                      ((SOURCE) == RCC_SYSCLKSource_HSE)   || \
                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK)|| \
                                      ((SOURCE) == RCC_SYSCLKSource_LSE)    || \
                                      ((SOURCE) == RCC_SYSCLKSource_LSI)     || \
                                      ((SOURCE) == RCC_SYSCLKSource_HSI48)   || \
                                      ((SOURCE) == RCC_SYSCLKSource_HSI12)   || \
                                      ((SOURCE) == RCC_SYSCLKSource_EXTCLK))




/**
  * @}
  */


/** @defgroup RCC_EXTCLK_GPIO_source RCC_EXTCLK_GPIO_source
  * @{
  */
#define RCC_EXTCLK_GPIO_PA4              ((uint32_t)0x00 << RCC_CFGR4_EXTCLK_SEL_Pos)
#define RCC_EXTCLK_GPIO_PA13             ((uint32_t)0x01 << RCC_CFGR4_EXTCLK_SEL_Pos)
#define RCC_EXTCLK_GPIO_PC4             ((uint32_t)0x02 << RCC_CFGR4_EXTCLK_SEL_Pos)
#define RCC_EXTCLK_GPIO_PA0              ((uint32_t)0x03 << RCC_CFGR4_EXTCLK_SEL_Pos)

#define IS_RCC_EXTCLK_GPIO(GPIOCLK) (((GPIOCLK) == RCC_EXTCLK_GPIO_PA4) || \
                                     ((GPIOCLK) == RCC_EXTCLK_GPIO_PA13)|| \
                                     ((GPIOCLK) == RCC_EXTCLK_GPIO_PA0)|| \
                                     ((GPIOCLK) == RCC_EXTCLK_GPIO_PC4))

/** @defgroup RCC_AHB_Clock_Source RCC_AHB_Clock_Source
  * @{
  */

#define RCC_SYSCLK_Div1                  ((uint32_t)0x00 << RCC_CFGR_HPRE_Pos)
#define RCC_SYSCLK_Div2                  ((uint32_t)0x08 << RCC_CFGR_HPRE_Pos)
#define RCC_SYSCLK_Div4                  ((uint32_t)0x09 << RCC_CFGR_HPRE_Pos)
#define RCC_SYSCLK_Div8                  ((uint32_t)0x0A << RCC_CFGR_HPRE_Pos)
#define RCC_SYSCLK_Div16                 ((uint32_t)0x0B << RCC_CFGR_HPRE_Pos)
#define RCC_SYSCLK_Div64                 ((uint32_t)0x0C << RCC_CFGR_HPRE_Pos)
#define RCC_SYSCLK_Div128                ((uint32_t)0x0D << RCC_CFGR_HPRE_Pos)
#define RCC_SYSCLK_Div256                ((uint32_t)0x0E << RCC_CFGR_HPRE_Pos)
#define RCC_SYSCLK_Div512                ((uint32_t)0x0F << RCC_CFGR_HPRE_Pos)
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
                           ((HCLK) == RCC_SYSCLK_Div512))
/**
  * @}
  */

/** @defgroup RCC_APB_Clock_Source RCC_APB_Clock_Source
  * @{
  */

#define RCC_HCLK_Div1                    ((uint32_t)0x00)
#define RCC_HCLK_Div2                    ((uint32_t)0x04)
#define RCC_HCLK_Div4                    ((uint32_t)0x05)
#define RCC_HCLK_Div8                    ((uint32_t)0x06)
#define RCC_HCLK_Div16                   ((uint32_t)0x07)
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
                           ((PCLK) == RCC_HCLK_Div16))
/**
  * @}
  */


/** @defgroup RCC_I2C_clock_source RCC_I2C_clock_source
  * @{
  */

#define RCC_I2C1CLK_HSI                   ((uint32_t)0x00000000)
#define RCC_I2C1CLK_SYSCLK                ((uint32_t)0x01 << RCC_CFGR4_I2C1CLKSW_Pos)
#define RCC_I2C1CLK_PCLk2                 ((uint32_t)0x02 << RCC_CFGR4_I2C1CLKSW_Pos)


#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI)    ||  \
                               ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \
                               ((I2CCLK) == RCC_I2C1CLK_PCLk2))


/**
  * @}
  */

/** @defgroup RCC_USART_clock_source RCC_USART_clock_source
  * @{
  */

#define RCC_UARTCLK_PCLK                  ((uint32_t)0x00)
#define RCC_UARTCLK_LSE                   ((uint32_t)0x01)
#define RCC_UARTCLK_LSI                   ((uint32_t)0x02)
#define RCC_UARTCLK_HSI12                 ((uint32_t)0x03)

#define IS_RCC_SELECTIONCLK(UARTCLK) (((UARTCLK) == RCC_UARTCLK_PCLK)   || \
                                      ((UARTCLK) == RCC_UARTCLK_LSE)    || \
                                      ((UARTCLK) == RCC_UARTCLK_LSI)    || \
                                      ((UARTCLK) == RCC_UARTCLK_HSI12))
/**
  * @}
  */

/** @defgroup RCC_ADC_clock_source  RCC_ADC_clock_source
  * @{
  */
#define RCC_ADCCLK_HSI12                  ((uint32_t)0x00)
#define RCC_ADCCLK_PCLKDiv2               ((uint32_t)0x01)
#define RCC_ADCCLK_PCLKDiv4               ((uint32_t)0x02)
#define RCC_ADCCLK_PCLK                   ((uint32_t)0x03)

#define IS_RCC_SELECTIONADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI12)   || \
                                       ((ADCCLK) == RCC_ADCCLK_PCLKDiv2) || \
                                       ((ADCCLK) == RCC_ADCCLK_PCLKDiv4) || \
                                       ((ADCCLK) == RCC_ADCCLK_PCLK))
/**
  * @}
  */

/** @defgroup RCC_FLITF_clock_source  RCC_FLITF_clock_source
  * @{
  */
#define RCC_FLITFCLK_HSI                  ((uint32_t)0x00)
#define RCC_FLITFCLK_SYSCLK               ((uint32_t)0x01)
#define RCC_FLITFCLK_EXTCLK               ((uint32_t)0x02)


#define IS_RCC_SELECTIONFLITFCLK(FLITFCLK) (((FLITFCLK) == RCC_FLITFCLK_HSI)     || \
                                            ((FLITFCLK) == RCC_FLITFCLK_SYSCLK)  || \
                                                                                        ((FLITFCLK) == RCC_FLITFCLK_EXTCLK))
/**
  * @}
  */


/** @defgroup RCC_FLITF_Prescaler_Factor  RCC_FLITF_Prescaler_Factor
  * @{
  */
#define   RCC_FLITF_Div1        ((uint32_t)0x00)
#define   RCC_FLITF_Div2        ((uint32_t)0x01)
#define   RCC_FLITF_Div3        ((uint32_t)0x02)
#define   RCC_FLITF_Div4        ((uint32_t)0x03)
#define   RCC_FLITF_Div5        ((uint32_t)0x04)
#define   RCC_FLITF_Div6        ((uint32_t)0x05)
#define   RCC_FLITF_Div7        ((uint32_t)0x06)
#define   RCC_FLITF_Div8        ((uint32_t)0x07)
#define   RCC_FLITF_Div9        ((uint32_t)0x08)
#define   RCC_FLITF_Div10       ((uint32_t)0x09)
#define   RCC_FLITF_Div11       ((uint32_t)0x0A)
#define   RCC_FLITF_Div12       ((uint32_t)0x0B)

#define IS_RCC_FLITFCLK_PREDIV(FLITFPREDIV) (((FLITFPREDIV) == RCC_FLITF_Div1)     || \
                                             ((FLITFPREDIV) == RCC_FLITF_Div2)     || \
                                                                                         ((FLITFPREDIV) == RCC_FLITF_Div3)     || \
                                                                                         ((FLITFPREDIV) == RCC_FLITF_Div4)     || \
                                                                                         ((FLITFPREDIV) == RCC_FLITF_Div5)     || \
                                                                                         ((FLITFPREDIV) == RCC_FLITF_Div6)     || \
                                                                                         ((FLITFPREDIV) == RCC_FLITF_Div7)     || \
                                                                                         ((FLITFPREDIV) == RCC_FLITF_Div8)     || \
                                                                                         ((FLITFPREDIV) == RCC_FLITF_Div9)     || \
                                                                                         ((FLITFPREDIV) == RCC_FLITF_Div10)     || \
                                                                                         ((FLITFPREDIV) == RCC_FLITF_Div11)     || \
                                                                                         ((FLITFPREDIV) == RCC_FLITF_Div12))
/**
  * @}
  */


/** @defgroup RCC_Interrupt_Source RCC_Interrupt_Source
  * @{
  */

#define RCC_IT_LSIRDY                    ((uint32_t)0x00000001)
#define RCC_IT_LSERDY                    ((uint32_t)0x00000002)
#define RCC_IT_HSIRDY                    ((uint32_t)0x00000004)
#define RCC_IT_HSERDY                    ((uint32_t)0x00000008)
#define RCC_IT_PLLRDY                    ((uint32_t)0x00000010)
#define RCC_IT_HSI12RDY                  ((uint32_t)0x00000020)
#define RCC_IT_LSEFAIL                   ((uint32_t)0x00000080)
#define RCC_IT_CSSHSE                    ((uint32_t)0x00800000)
#define RCC_IT_CSSLSE                    ((uint32_t)0x80000000)


#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
                           ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
                           ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI12RDY) || \
                           ((IT) == RCC_IT_LSEFAIL)||  ((IT) == RCC_IT_CSSHSE) || \
                           ((IT) == RCC_IT_CSSLSE))

#define IS_RCC_IT(IT) ((((IT) & (uint32_t)0x3F404040) == 0x00) && ((IT) != 0x00))
#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)

/**
  * @}
  */

/** @defgroup RCC_LSE_Configuration RCC_LSE_Configuration
  * @{
  */

#define RCC_LSE_OFF                      ((uint32_t)0x00000000)
#define RCC_LSE_ON                       RCC_LSECTLR_LSEON
#define RCC_LSE_Bypass                   ((uint32_t)(RCC_LSECTLR_LSEON | RCC_LSECTLR_LSEBYP))
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
                         ((LSE) == RCC_LSE_Bypass))
/**
  * @}
  */

/** @defgroup RCC_RTC_Clock_Source RCC_RTC_Clock_Source
  * @{
  */

#define RCC_RTCCLKSource_LSE             RCC_BDCR_RTCSEL_0
#define RCC_RTCCLKSource_LSI             RCC_BDCR_RTCSEL_1
#define RCC_RTCCLKSource_HSE_Div32       RCC_BDCR_RTCSEL

#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
/**
  * @}
  */

/** @defgroup RCC_LSE_Drive_Configuration RCC_LSE_Drive_Configuration
  * @{
  */

#define RCC_LSEDrive_LEVEL0              ((uint32_t)0x00000000)
#define RCC_LSEDrive_LEVEL1              ((uint32_t)0x01 << RCC_LSECNT_LSE_CNT_LOWER_LIMIT_Pos)
#define RCC_LSEDrive_LEVEL2              ((uint32_t)0x02 << RCC_LSECNT_LSE_CNT_LOWER_LIMIT_Pos)
#define RCC_LSEDrive_LEVEL3              ((uint32_t)0x03 << RCC_LSECNT_LSE_CNT_LOWER_LIMIT_Pos)
#define RCC_LSEDrive_LEVEL4              ((uint32_t)0x04 << RCC_LSECNT_LSE_CNT_LOWER_LIMIT_Pos)
#define RCC_LSEDrive_LEVEL5              ((uint32_t)0x05 << RCC_LSECNT_LSE_CNT_LOWER_LIMIT_Pos)
#define RCC_LSEDrive_LEVEL6              ((uint32_t)0x06 << RCC_LSECNT_LSE_CNT_LOWER_LIMIT_Pos)
#define RCC_LSEDrive_LEVEL7              ((uint32_t)0x07 << RCC_LSECNT_LSE_CNT_LOWER_LIMIT_Pos)

#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_LEVEL0) || \
                                 ((DRIVE) == RCC_LSEDrive_LEVEL1) || \
                                 ((DRIVE) == RCC_LSEDrive_LEVEL2) || \
                                 ((DRIVE) == RCC_LSEDrive_LEVEL3) || \
                                 ((DRIVE) == RCC_LSEDrive_LEVEL4) || \
                                 ((DRIVE) == RCC_LSEDrive_LEVEL5) || \
                                 ((DRIVE) == RCC_LSEDrive_LEVEL6) || \
                                 ((DRIVE) == RCC_LSEDrive_LEVEL7))
/**
  * @}
  */

/** @defgroup RCC_AHB_Peripherals RCC_AHB_Peripherals
  * @{
  */

#define RCC_AHBPeriph_GPIOA               RCC_AHBENR_IOPAEN
#define RCC_AHBPeriph_GPIOB               RCC_AHBENR_IOPBEN
#define RCC_AHBPeriph_GPIOC               RCC_AHBENR_IOPCEN
#define RCC_AHBPeriph_GPIOF               RCC_AHBENR_IOPFEN
#define RCC_AHBPeriph_EMACC               RCC_AHBENR_EMACCEN
#define RCC_AHBPeriph_DIVSQ               RCC_AHBENR_DVSQEN
#define RCC_AHBPeriph_CRC                 RCC_AHBENR_CRCEN
#define RCC_AHBPeriph_FLITF               RCC_AHBENR_FLITFEN
#define RCC_AHBPeriph_SRAM                RCC_AHBENR_SRAMEN
#define RCC_AHBPeriph_DMA1                RCC_AHBENR_DMA1EN


#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFF1C0EA) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFFF1FCFE) == 0x00) && ((PERIPH) != 0x00))

/**
  * @}
  */

/** @defgroup RCC_APB2_Peripherals RCC_APB2_Peripherals
  * @{
  */

#define RCC_APB2Periph_I2C1            RCC_APB2ENR_I2C1EN
#define RCC_APB2Periph_COMP            RCC_APB2ENR_COMPEN
#define RCC_APB2Periph_OPAMP           RCC_APB2ENR_OPAMPEN
#define RCC_APB2Periph_CAN             RCC_APB2ENR_CANEN
#define RCC_APB2Periph_DBG             RCC_APB2ENR_DBGEN
#define RCC_APB2Periph_TIM14           RCC_APB2ENR_TIM14EN
#define RCC_APB2Periph_TIM3            RCC_APB2ENR_TIM3EN
#define RCC_APB2Periph_UART6           RCC_APB2ENR_UART6EN
#define RCC_APB2Periph_UART4           RCC_APB2ENR_UART4EN
#define RCC_APB2Periph_TIM2            RCC_APB2ENR_TIM2EN
#define RCC_APB2Periph_UART3           RCC_APB2ENR_UART3EN
#define RCC_APB2Periph_TIM1            RCC_APB2ENR_TIM1EN
#define RCC_APB2Periph_UART2           RCC_APB2ENR_UART2EN
#define RCC_APB2Periph_SYSCFG          RCC_APB2ENR_SYSCFGEN

#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFC568) == 0x00) && ((PERIPH) != 0x00))

/**
  * @}
  */


/** @defgroup RCC_APB1_Peripherals RCC_APB1_Peripherals
  * @{
  */

#define RCC_APB1Periph_PWR               RCC_APB1ENR_PWREN
#define RCC_APB1Periph_SPI1              RCC_APB1ENR_SPI1EN
#define RCC_APB1Periph_WWDG              RCC_APB1ENR_WWDGEN
#define RCC_APB1Periph_UART1             RCC_APB1ENR_UART1EN
#define RCC_APB1Periph_TIM6              RCC_APB1ENR_TIM6EN
#define RCC_APB1Periph_RTC               RCC_APB1ENR_RTCEN
#define RCC_APB1Periph_ADC               RCC_APB1ENR_ADCEN


#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xFBFF6FC6) == 0x00) && ((PERIPH) != 0x00))
/**
  * @}
  */

/** @defgroup RCC_MCO_Clock_Source RCC_MCO_Clock_Source
  * @{
  */

#define RCC_MCOSource_NoClock            ((uint8_t)0x00)
#define RCC_MCOSource_HSI12              ((uint8_t)0x01)
#define RCC_MCOSource_LSI                ((uint8_t)0x02)
#define RCC_MCOSource_LSE                ((uint8_t)0x03)
#define RCC_MCOSource_SYSCLK             ((uint8_t)0x04)
#define RCC_MCOSource_HSI                ((uint8_t)0x05)
#define RCC_MCOSource_HSE                ((uint8_t)0x06)
#define RCC_MCOSource_PLLCLK             ((uint8_t)0x07)


#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI12)      || \
                                   ((SOURCE) == RCC_MCOSource_SYSCLK)  || ((SOURCE) == RCC_MCOSource_HSI)        || \
                                   ((SOURCE) == RCC_MCOSource_HSE)     || ((SOURCE) == RCC_MCOSource_PLLCLK)|| \
                                   ((SOURCE) == RCC_MCOSource_LSI)     || ((SOURCE) == RCC_MCOSource_LSE))
/**
  * @}
  */

/** @defgroup EMACC_trace_clk_prediv  EMACC_trace_clk_prediv
  * @{
  */
#define EMACC_Trace_DIV_1        ((uint32_t)0x00 << RCC_AHBENR_TRACE_UART_PREDIV_Pos)
#define EMACC_Trace_DIV_2        ((uint32_t)0x01 << RCC_AHBENR_TRACE_UART_PREDIV_Pos)
#define EMACC_Trace_DIV_3        ((uint32_t)0x02 << RCC_AHBENR_TRACE_UART_PREDIV_Pos)
#define EMACC_Trace_DIV_4        ((uint32_t)0x03 << RCC_AHBENR_TRACE_UART_PREDIV_Pos)
#define EMACC_Trace_DIV_5        ((uint32_t)0x04 << RCC_AHBENR_TRACE_UART_PREDIV_Pos)
#define EMACC_Trace_DIV_6        ((uint32_t)0x05 << RCC_AHBENR_TRACE_UART_PREDIV_Pos)
#define EMACC_Trace_DIV_7        ((uint32_t)0x06 << RCC_AHBENR_TRACE_UART_PREDIV_Pos)
#define EMACC_Trace_DIV_8        ((uint32_t)0x07 << RCC_AHBENR_TRACE_UART_PREDIV_Pos)
#define EMACC_Trace_DIV_9        ((uint32_t)0x08 << RCC_AHBENR_TRACE_UART_PREDIV_Pos)
#define EMACC_Trace_DIV_10       ((uint32_t)0x09 << RCC_AHBENR_TRACE_UART_PREDIV_Pos)
#define EMACC_Trace_DIV_11       ((uint32_t)0x0A << RCC_AHBENR_TRACE_UART_PREDIV_Pos)
#define EMACC_Trace_DIV_12       ((uint32_t)0x0B << RCC_AHBENR_TRACE_UART_PREDIV_Pos)
#define EMACC_Trace_DIV_13       ((uint32_t)0x0C << RCC_AHBENR_TRACE_UART_PREDIV_Pos)
#define EMACC_Trace_DIV_14       ((uint32_t)0x0D << RCC_AHBENR_TRACE_UART_PREDIV_Pos)
#define EMACC_Trace_DIV_15       ((uint32_t)0x0E << RCC_AHBENR_TRACE_UART_PREDIV_Pos)
#define EMACC_Trace_DIV_16       ((uint32_t)0x0F << RCC_AHBENR_TRACE_UART_PREDIV_Pos)

#define IS_RCC_EMACC_TRACE_DIV(TRACE_CLKDIV)     (((TRACE_CLKDIV) == EMACC_Trace_DIV_1) || ((TRACE_CLKDIV) == EMACC_Trace_DIV_2) || \
                                                  ((TRACE_CLKDIV) == EMACC_Trace_DIV_3) || ((TRACE_CLKDIV) == EMACC_Trace_DIV_4) || \
                                                  ((TRACE_CLKDIV) == EMACC_Trace_DIV_5) || ((TRACE_CLKDIV) == EMACC_Trace_DIV_6) || \
                                                  ((TRACE_CLKDIV) == EMACC_Trace_DIV_7) || ((TRACE_CLKDIV) == EMACC_Trace_DIV_8) || \
                                                  ((TRACE_CLKDIV) == EMACC_Trace_DIV_9) || ((TRACE_CLKDIV) == EMACC_Trace_DIV_10) || \
                                                  ((TRACE_CLKDIV) == EMACC_Trace_DIV_11) || ((TRACE_CLKDIV) == EMACC_Trace_DIV_12) || \
                                                  ((TRACE_CLKDIV) == EMACC_Trace_DIV_13) || ((TRACE_CLKDIV) == EMACC_Trace_DIV_14) || \
                                                  ((TRACE_CLKDIV) == EMACC_Trace_DIV_15) || ((TRACE_CLKDIV) == EMACC_Trace_DIV_16))


/**
  * @}
  */
/** @defgroup RCC_MCOPrescaler RCC_MCOPrescaler
  * @{
  */

#define RCC_MCOPrescaler_1            ((uint32_t)0x00 << RCC_CFGR_MCOPRE_Pos)
#define RCC_MCOPrescaler_2            ((uint32_t)0x01 << RCC_CFGR_MCOPRE_Pos)
#define RCC_MCOPrescaler_4            ((uint32_t)0x02 << RCC_CFGR_MCOPRE_Pos)
#define RCC_MCOPrescaler_8            ((uint32_t)0x03 << RCC_CFGR_MCOPRE_Pos)
#define RCC_MCOPrescaler_16           ((uint32_t)0x04 << RCC_CFGR_MCOPRE_Pos)
#define RCC_MCOPrescaler_32           ((uint32_t)0x05 << RCC_CFGR_MCOPRE_Pos)
#define RCC_MCOPrescaler_64           ((uint32_t)0x06 << RCC_CFGR_MCOPRE_Pos)
#define RCC_MCOPrescaler_128          ((uint32_t)0x07 << RCC_CFGR_MCOPRE_Pos)

#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1)  || \
                                         ((PRESCALER) == RCC_MCOPrescaler_2)  || \
                                         ((PRESCALER) == RCC_MCOPrescaler_4)  || \
                                         ((PRESCALER) == RCC_MCOPrescaler_8)  || \
                                         ((PRESCALER) == RCC_MCOPrescaler_16) || \
                                         ((PRESCALER) == RCC_MCOPrescaler_32) || \
                                         ((PRESCALER) == RCC_MCOPrescaler_64) || \
                                         ((PRESCALER) == RCC_MCOPrescaler_128))

/**
  * @}
  */

/** @defgroup RCC_Flag RCC_Flag
  * @{
  */
#define RCC_FLAG_HSIRDY                  ((uint8_t)0x01)
#define RCC_FLAG_HSERDY                  ((uint8_t)0x11)
#define RCC_FLAG_PLLRDY                  ((uint8_t)0x19)
#define RCC_FLAG_LSERDY                  ((uint8_t)0x21)
#define RCC_FLAG_LSIRDY                  ((uint8_t)0x41)
#define RCC_FLAG_OBLRST                  ((uint8_t)0x59)
#define RCC_FLAG_PINRST                  ((uint8_t)0x5A)
#define RCC_FLAG_PORRST                  ((uint8_t)0x5B)
#define RCC_FLAG_SFTRST                  ((uint8_t)0x5C)
#define RCC_FLAG_IWDGRST                 ((uint8_t)0x5D)
#define RCC_FLAG_WWDGRST                 ((uint8_t)0x5E)
#define RCC_FLAG_LPWRRST                 ((uint8_t)0x5F)
#define RCC_FLAG_HSI12RDY                ((uint8_t)0x61)
#define RCC_FLAG_HSI48RDY                ((uint8_t)0x70)

#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
                           ((FLAG) == RCC_FLAG_PLLRDY)  || ((FLAG) == RCC_FLAG_LSERDY)  || \
                           ((FLAG) == RCC_FLAG_LSIRDY)  || ((FLAG) == RCC_FLAG_OBLRST)  || \
                           ((FLAG) == RCC_FLAG_PINRST)  || ((FLAG) == RCC_FLAG_PORRST)  || \
                           ((FLAG) == RCC_FLAG_SFTRST)  || ((FLAG) == RCC_FLAG_IWDGRST) || \
                           ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST) || \
                           ((FLAG) == RCC_FLAG_HSI12RDY)|| \
                           ((FLAG) == RCC_FLAG_HSI48RDY))

#define IS_RCC_HSI_FINETRIM_VALUE(VALUE) ((VALUE) <= 0x3F)
#define IS_RCC_HSI_COARSETRIM_VALUE(VALUE) ((VALUE) <= 0x3F)
#define IS_RCC_LSI_TRIM_VALUE(VALUE)       ((VALUE) <= 0x3F)
#define IS_CSS_THRESHOLD_VALUE(VALUE)   ((VALUE) <= 0x7F)

/**
  * @}
  */

/**
  * @}
  */
/** @defgroup RCC_Function_Declaration RCC_Function_Declaration
  * @{
  */
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */

/* Function used to set the RCC clock configuration to the default reset state */
void RCC_DeInit(void);

/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
void RCC_HSEConfig(uint8_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);

void RCC_HSICOARSETRIM(uint8_t HSICOARSETRIMValue);
void RCC_HSIFineTRIM(uint8_t HSIFINETRIMValue);
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);

void RCC_HSICmd(FunctionalState NewState);

void RCC_HSI12Cmd(FunctionalState NewState);
void RCC_LSEConfig(uint32_t RCC_LSE);
void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
void RCC_LSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_HSI48Cmd(FunctionalState NewState);
void RCC_PREDIVConfig(uint32_t RCC_PREDIV_Div);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler);

/* System, AHB and APB busses clocks configuration functions ******************/
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_I2C1CLKConfig(uint32_t RCC_I2C1CLK);
void RCC_UART1CLKConfig(uint32_t RCC_UARTCLK);
void RCC_UART2CLKConfig(uint32_t RCC_UARTCLK);
void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK);

void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks);

/* Peripheral clocks configuration functions **********************************/
void RCC_LSECTLRResetCmd(FunctionalState NewState);
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);

void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);

/* Interrupts and flags management functions **********************************/
void RCC_ITConfig(uint32_t RCC_IT, FunctionalState NewState);
FlagStatus RCC_GetFlagStatus(uint32_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint32_t RCC_IT);
void RCC_ClearITPendingBit(uint32_t RCC_IT);
void RCC_LSEWTConfig(uint8_t LSEWT_Value);
void RCC_CSS_THRESHOLD_Config(uint8_t CSS_THRESHOLD_Value);
void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
void RCC_HSI48ADCRequestCmd(FunctionalState NewState);
void RCC_EXTCLK_GPIO_Config(uint32_t RCC_EXTCLK_GPIO);
void RCC_EMACC_Trace_Baute(uint16_t TRACE_CLKDIV);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
/**
  * @}
  */
#ifdef __cplusplus
}
#endif

#endif /* __MYG0025_RCC_H */

/**
  * @}
  */

/**
  * @}
  */






